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ESD Stress Effect on Failure Mechanisms in GaN-on-Si Power Device
发布时间：2024-09-25
浏览次数：300 次
成果介绍
Abstract—This paper reports investigation of failure mechanisms of GaN-on-Si power device under electrostatic discharge (ESD) stress using on-wafer transmission-line pulse (TLP)
testing. Hot-hole injections under the gate and filament formation
in the buffer layer are examined by monitoring the threshold voltage (Vth) and on-resistance (Ron) subjected to a floating gate or
an off-state gate voltage. Distinct and continued degradation has
been observed after the ESD stress is removed indicating a slow
de-trapping process due to deep-level buffer traps. Finally, 2D
device simulation is used to probe the physical insight into failure
mechanisms.
Index Terms—Buffer traps, electrostatic discharge, failure
mechanisms, GaN-on-Si, transmission-line pulse.
testing. Hot-hole injections under the gate and filament formation
in the buffer layer are examined by monitoring the threshold voltage (Vth) and on-resistance (Ron) subjected to a floating gate or
an off-state gate voltage. Distinct and continued degradation has
been observed after the ESD stress is removed indicating a slow
de-trapping process due to deep-level buffer traps. Finally, 2D
device simulation is used to probe the physical insight into failure
mechanisms.
Index Terms—Buffer traps, electrostatic discharge, failure
mechanisms, GaN-on-Si, transmission-line pulse.
应用领域
半导体
团队介绍
Wen Yang , Member, IEEE, Nicholas Stoll, Student Member, IEEE,
and Jiann-Shiun Yuan , Senior Member, IEEE
and Jiann-Shiun Yuan , Senior Member, IEEE
成果图片
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专家信息
教授
单位：华南理工大学
院系：华南理工大学
团队成员：
